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| MC74HC139A Dual 1-of-4 Decoder/ Demultiplexer High-Performance Silicon-Gate CMOS The MC74HC139A is identical in pinout to the LS139. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. This device consists of two independent 1-of-4 decoders, each of which decodes a two-bit Address to one-of-four active-low outputs. Active-low Selects are provided to facilitate the demultiplexing and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and utilizing the Select as a data input. http://onsemi.com MARKING DIAGRAMS 16 16 1 * * * * * * * MC74HC139AN AWLYYWW 1 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 100 FETs or 25 Equivalent Gates PDIP-16 N SUFFIX CASE 648 16 16 1 HC139A AWLYWW 1 SO-16 D SUFFIX CASE 751B SELECTa A0a A1a Y0a Y1a Y2a Y3a GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC SELECTb A0b A1b Y0b Y1b Y2b Y3b A L, WL Y, YY W, WW = Assembly Location = Wafer Lot = Year = Work Week 16 16 1 TSSOP-16 DT SUFFIX CASE 948F HC 139A ALYW 1 Figure 1. Pin Assignment FUNCTION TABLE Inputs Select H L L L L A1 X L L H H A0 X L H L H Y0 H L H H H Outputs Y1 Y2 H H L H H H H H L H Y3 H H H H L ORDERING INFORMATION Device MC74HC139AN MC74HC139AD MC74HC139ADR2 MC74HC139ADT MC74HC139ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000/Box 48/Rail 2500/Reel 96/Rail 2500/Reel X = don't care (c) Semiconductor Components Industries, LLC, 2001 1 June, 2001 - Rev. 8 Publication Order Number: MC74HC139A/D MC74HC139A ADDRESS INPUTS A0a A1a 2 3 4 5 6 7 Y0a Y1a Y2a Y3a PIN 16 = VCC PIN 8 = GND ACTIVE-LOW OUTPUTS SELECTa ADDRESS INPUTS A0b A1b 1 14 13 12 11 10 9 Y0b Y1b Y2b Y3b ACTIVE-LOW OUTPUTS SELECTb 15 Figure 2. Logic Diagram http://onsemi.com 2 MC74HC139A MAXIMUM RATINGS (Note 1) Symbol VCC VIN VOUT IIN IOUT ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP Parameter (Referenced to GND) (Referenced to GND) (Referenced to GND) (Note 2) Value *0.5 to )7.0 *1.5 to VCC )1.5 *0.5 to VCC )0.5 $20 $25 $50 $50 *65 to )150 260 )150 78 112 148 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 85_C (Note 6) UL-94-VO (0.125 in) u2000 u200 u1000 $300 V Unit V V V mA mA mA mA _C _C _C _C/W PD Power Dissipation in Still Air at 85_C mW MSL FR VESD Moisture Sensitivity Flammability Rating ESD Withstand Voltage ILATCH-UP Latch-Up Performance mA 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. 2. IO absolute maximum rating must be observed. 3. Tested to EIA/JESD22-A114-A. 4. Tested to EIA/JESD22-A115-A. 5. Tested to JESD22-C101-A. 6. Tested to EIA/JESD78. 7. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC DC Supply Voltage Parameter (Referenced to GND) Min 2.0 0 Max 6.0 Unit V V III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I VIN, V OUT TA DC Input Voltage, Output Voltage (Referenced to GND) VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) *55 0 0 0 )125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 8. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level. http://onsemi.com 3 MC74HC139A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions VOUT = 0.1 V or VCC *0.1 V |IOUT| v 20 mA VOUT = 0.1 V or VCC *0.1 V |IOUT| v 20 mA V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Guaranteed Limit *55_C to 25_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 v85_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 v125_C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 Unit V II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII VIL Maximum Low-Level Input Voltage V VOH Minimum High-Level Output Voltage VIN = VIH or VIL |IOUT| v 20 mA VIN = VIH or VIL V |IOUT| v 4.0 mA |IOUT| v 5.2 mA 3.98 5.48 0.1 0.1 0.1 3.84 5.34 0.1 0.1 0.1 3.70 5.20 0.1 0.1 0.1 VOL Maximum Low-Level Output Voltage VIN = VIH or VIL |IOUT| v 20 mA VIN = VIH or VIL V |IOUT| v 4.0 mA |IOUT| v 5.2 mA 0.26 0.26 0.33 0.33 0.40 0.40 IIN Maximum Input Leakage Current VIN = VCC or GND VIN = VCC or GND IOUT = 0 mA $0.1 4 $1.0 40 $1.0 160 mA mA ICC Maximum Quiescent Supply Current (per Package) 9. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Select to Output Y (Figures 1 and 3) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - Guaranteed Limit *55_C to 25_C 115 23 20 115 23 20 75 15 13 10 v85_C 145 29 25 145 29 25 95 19 16 10 v125_C 175 35 30 175 35 30 110 22 19 10 Unit ns II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Maximum Propagation Delay, Input A to Output Y (Figures 2 and 3) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance ns ns pF 10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Decoder) (Note 11) 55 pF 11. Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f ) I CC V CC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC139A tf 90% 50% SELECT 10% tPHL 90% 50% 10% tPLH tr VCC GND INPUT A tPLH OUTPUT Y tTLH 50% VALID 50% GND tPHL VALID VCC OUTPUT Y tTHL Figure 3. Switching Waveform Figure 4. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance Figure 5. Test Circuit http://onsemi.com 5 MC74HC139A PIN DESCRIPTIONS ADDRESS INPUTS A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13) inputs. A high level on this input forces all outputs to a high level. OUTPUTS Y0a - Y3a, Y0b - Y3b (Pins 4 - 7, 12, 11, 10, 9) Address inputs. These inputs, when the respective 1-of-4 decoder is enabled, determine which of its four active-low outputs is selected. CONTROL INPUTS Selecta, Selectb (Pins 1, 15) Active-low outputs. These outputs assume a low level when addressed and the appropriate Select input is active. These outputs remain high when not addressed or the appropriate Select input is inactive. Active-low select inputs. For a low level on this input, the outputs for that particular decoder follow the Address SELECT Y0 Y1 A0 Y2 Y3 A1 Figure 6. Expanded Logic Diagram (1/2 of Device) http://onsemi.com 6 MC74HC139A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 7 MC74HC139A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.15 (0.006) T U S 0.25 (0.010) M A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 EEE CCC EEE CCC -W- MC74HC139A/D |
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